Last update on Dec.7, 2018, to get a more up-to-date list of publications, please visit Miao Hu's Google Scholar Website.

A. LIst of Publications

(i). Book Chapters

1. H. Li and M. Hu, "Modeling of Memristor at nanoscale: Static, Statistical, and Stochastic methodologies," a book chapter in CMOS and Post-CMOS Perspectives of Electronic Device Scaling, edited by Saraju Mohanty, Springer, 2015.

(ii). Journal Articles

1. [Advanced materials] M. Hu, et.al, "Analog computation and neural network classification with a dot product engine," Advanced materials, vol. 30, no. 9, pp.1705914, Mar. 2018.

2. [TCAD] M. Hu, Y. Chen, J. Joshua Yang, Y. Wang, H. Li, "A Memristor-based Dynamic Synapse for Spiking Neural Networks," IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, vol. pp, no 99, pp. 1-1, Oct. 2016.

3. [TNNLS] M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose and W. Linerman, "Memristor Crossbar Based Neuromorphic Computing System: A Case Study," IEEE Transactions on Neural Network and Learning System, vol. 25, no 10, pp. 1864-1878, Oct. 2014.

4. [JOLPE] M. Hu, H. Li, Y. Chen, and X. Wang, "Spintronic Memristor: Compact Model and Statistical Analysis," Journal of Low Power Electronics, vol. 7, no 2, pp. 234-244, Apr. 2011.

5. [Nature communications] Z. Wang, M. Rao, J. Han, ..., M. Hu, ..., J. J. Yang, "Capacitive neural network with neuro-transistors," Nature communications, vol.9, no.1, pp.3208, Aug. 2018.

6. [Nature communications] C. Li, D. Belkin, Y. Li, P. Yan, M. Hu, et al., "Efficient and self-adaptive in-situ learning in multilayer memristor neural networks," Nature Communications, vol.9, no.1, pp.2385, Jun. 2018.

7. [Nature electronics] Z. Wang, S. Joshi, ..., M. Hu, ..., J.J. Yang, "Fully memristive neural networks for pattern classification with unsupervised learning," Nature electronics, vol. 1, no. 2, pp. 137, Feb. 2018.

8. [Nature electronics] Z. Wang, S. Joshi, ..., M. Hu, ..., J.J. Yang, "Diffusive memristor artificial neurons for fully memristive neural network," Nature electronics, In Press.

9. [Nature electronics] C. Li, M. Hu, ... Q. Xia, "Analog signal and image processing with large memristor crossbars," Nature electronics, vol. 1, no.1, pp. 52, Jan. 2018.

10. [Scientific reports] N. Ge, J. H. Yoon, M. Hu, et al., "An Efficient Analog Hamming Distance Comparator Realized with A Unipolar Memristor Array: A Showcase of Physical Computing," accepted by Scientific Reports, Nov. 2016.

11. [Nature materials] Z. Wang, S. Joshi, S. E. Savelev, H. Jiang, R. Midya, P. Lin, M. Hu, et al., "Memristros with diffusive dynamics as synaptic emulators for neuromorphic computing," Nature materials, Sep. 2016.

12. [Advanced electronic materials] K. Min Kim, J. Joshua Yang, E. Merced, C. Grave, S. Lam, N. Davila, M. Hu, et al., "Low Variability Resistor-Memristor Circuit Masking the Actual Memristor States, " Advanced electronic materials, vol. 1, no. 6, Jun. 2015.

(iii). Conference Publications

1. [arXiv] Z. Fan, and M. Hu. "Memristor-based Deep Convolution Neural Network: A Case Study." arXiv preprint arXiv:1810.02225 (2018)..

2. [ICRC] M. Hu, J. P. Strachan, "Accelerating Discrete Fourier Transforms with Dot-product engine," IEEE International Conference on Rebooting Computing, pp. 1-5, Oct. 17-19, 2016.

3. [DAC] M. Hu, J. P. Strachan, Z. Li, E. M. Grafals, N. Davila, C. Graves,S. Lam, N. Ge, J. J. Yang and R. S. Williams, "Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication," 53rd ACM/EDAC/IEEE Design Automation Conference, pp.1-6, Jun. 5-9, 2016.

4. [ISQED] M. Hu, John Paul Strachan, Zhiyong Li and R. Stanley. "Dot-product engine as computing memory to accelerate machine learning algorithms," 17th International Symposium on Quality Electronic Design, pp. 374-379, Mar. 2016.

5. [HP Tech Con] M. Hu, J. P. Strachan and Z. Li, "Optimizing Memristor Crossbar for Next Generation Computing," HP internal technical conference Tech Con'15, June 2015. (130 accepted /1714 submissions, 7.6% acceptance rate)

6. [ASPDAC] M. Hu, Y. Wang, Q. Qiu, Y. Chen, and H. Li, "The Stochastic Modeling of TiO₂ Memristor and Its Usage in Neuromorphic System Design," the 19th Asia and South Pacific Design Automation Conference, Jan. 2014, pp. 831-836.

7. [CISDA] M. Hu, H. Li, Y. Chen, Q. Wu and G. S. Rose, "BSB Training Scheme Implementation on Memristor-Based Circuit," IEEE Symposium on Computational Intelligence for Security and Defense Applications, Apr. 2013.

8. [IJCNN](Invited) M. Hu, H. Li, Q. Wu, G. S. Rose and Yiran Chen, "Memristor Crossbar Based Hardware Realization of BSB Recall Function," International Joint Conference on Neural Networks, pp. 1, Jun. 2012.

9. [DAC] M. Hu, H. Li, Q. Wu, and G. S. Rose, "Hardware Realization of BSB Recall Function Using Memristor Crossbar Arrays," 49th Annual Design Automation Conference, pp. 498-503, Jun. 2012.

10. [ICCAD] M. Hu, H. Li, and R. E. Pino, "Fast Statistical Model of TiO2 Thin-Film Memristor and Design Implication," International Conference on Computer-Aided Design, pp.345-352, Nov. 2011.

11. [ASPDAC] M. Hu, H. Li, Y. Chen, and X. Wang, "Geometry Variations Analysis of TiO2-based and Spintronic Memristors," Proceedings of the 16th Asia and South Pacific Design Automation Conference, pp. 25-30, Jan. 2011. (Best paper nomination)

12. [arXiv] C. Li, Z. Wang, ..., M. Hu, ..., Q. Xia, "Long short-term memory networks in memristor crossbars," arXiv: 1805. 11801, 2018.

13. [ISCAS] C. Li, Y. Li, ..., M. Hu, ..., Q. Wu, "Large Memristor Crossbars for Analog Computing," IEEE International Conference on Circuits and Systems (ISCAS), pp. 1-4, 2018.

14. [DAC] C. Liu, M. Hu, J. P. Strachan, H. Li, "Rescuing memristor-based neuromorphic design with high defects," Proceedings of the 54^th Annual Design Automation Conference, pp. 87, 2017.

15. [ISCA] A. Shafiee, N. Anirban, N. Muralimanohar, R. Balasubramonian, J. P. Strachan, M. Hu, et al., "ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars," Proceedings of the 43rd International Symposium on Computer Architecture, Jun. 2016.

16. [HP Tech Con] N. Muralimanohar, J. P. Strachan, A. Sharma, B. Buchanan, M. Hu, et al., "A Scalable Architecture Using Dot-Product Engine to Accelerate Scientific Workloads," HP internal technical conference Tech Con'16, June 2016.

17. [HP Tech Con] G. Gibson, S. Musunuru, J. Zhang, K. Vandenberghe, M. Hu, et al., "Improved Selectors That Enable New Memristor Opportunities," HP internal technical conference Tech Con'16, June 2016.

18. [GLSVLSI] Y. Wang, W. Wen, M. Hu, Hai Li, "A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology," Proceedings of the 25th edition on Great Lakes Symposium on VLSI (GLSVLSI), pp. 271-276, May 2015.

19. [ISVLSI] H. Li, M. Hu, C. Li, and S. Duan, "Memristor Modeling �C Static, Statistical, and Stochastic Methodolo-gies," IEEE Computer Society Annual Symposium on VLSI, Jul. 2014.

20. [SiPS] Q. Qiu, Z. Li, K. Ahmed, H. Li, and M. Hu, "Neuromorphic Acceleration for Context Aware Text Image Recognition," IEEE International Workshop on Signal Processing Systems (SiPS), pp. 1-6, Oct. 2014.

21. [SoCC] H. Li, M. Hu, et al., "Emerging Memristor Technology Enabled Next Gen-eration Cortical Processor," the 27th IEEE International SoC Conference (SoCC), Sep. 2014.

22. [CODES+ISSS] B. Liu, M. Hu, H. Li, Y. Chen and J. Xue, "Bio-inspired Ultra Lower-power Neuromorphic Computing Engine for Embedded Systems," International Conference on Hardware/Software Codesign and System Synthesis, Oct. 2013.

23. [ISLPED] B. Li, Y. Shan, M. Hu, Y. Wang, Y. Chen, H. Yang, "Memristor-based approximated computation," International Symposium on Low Power Electronics and Design, pp. 242-247, Sep. 2013.

24. [DAC] B. Liu, M. Hu, H. Li, Z.-H. Mao, Y. Chen, T. Huang, and W. Zhang, "Digital-Assisted Noise Eliminating Training For Memristor Crossbar-Based Analog Neuromorphic Computing Engine," Proceedings of the 50^th Annual Design Automation Conference, Jun. 2013.

25. [DAC] RE. Pino, H. Li, Y. Chen, M. Hu and B. Liu, "Statistical memristor modeling and case study in neuromorphic computing," 49^th Annual Design Automation Conference, pp. 585- 590, Jun. 2012.

26. [DATE] H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," Design, Automation & Test in Europe Conference and Exhibition, pp. 673-678, Mar. 2010.

(iv). Peer Reviewed Conference abstract and Workshop Publications

1. M. Hu, Q. Xia, J. J. Yang, R. S. Williams, and J. P. Strachan, "Experimental demonstration of software-trained neural network inferencing in analog memristor crossbar arrays," lighting talk at Neuro-Inspired Computational Elements (NICE) Workshop, Mar. 2017.

2. M. Hu, J. P. Strachan, E. Merced-Grafals, Z. Li and R. S. Williams, "Dot-product Engine for Deep Learning, " ICCAD workshop on Hardware and Algorithms for Learning On-a-chip (HALO), Nov. 2015.

3. M. Hu, J. P. Strachan, E. Merced-Grafals, Z. Li and R. S. Williams, "Dot-Product Engine: Programming Memristor Crossbar Arrays for Efficient Vector-Matrix Multiplication," ICCAD workshop on Towards Efficient Computing in the Dark Silicon Era, Nov. 2015.

4. M. Hu and H. Li, "The Stochastic Characteristics of Memristor Devices and Case Studies in Neuromorphic Hardware Design," International Semiconductor Device Research Symposium (ISDRS), Dec. 2013.

5. M. Hu, H. Li, G. Rose, Q. Wu, and Y. Chen, "Training Scheme Analysis for Memristor-Based Neuromor-phic Design," International Workshop on Neuromorphic and Brain-Based Computing Systems (NeuComp) collocated with Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2013.

6. M. Hu and H. Li, "Low Power Neuromorphic Circuit Using Memristor Crossbar Array," ACM Student Research Competition at the 49th Design Automation Conference (DAC), Jun. 2012.

7. M. Hu, H. Li, and Y. Chen, "Statistical Model of TiO2 memristor," Working in Progress (WIP) by Design Automation Conference (DAC), Jun. 2011.

8. C. Li, D. Belkin, Y. Li, P. Yan, M. Hu, et al., "In-Memory Computing with Memristor Arrays," IEEE international memory workshop (IMW), pp, 1-4, 2018.

(v). Invited Presentations

1. "Using Conversion Algorithm to Compensate Errors in Analog Computing via Nano-crossbar," IRDS Emerging Research Devices and Architectures NanoCrossbar Workshop, Santa Clara, Jul. 15, 2016.

2. "Dot-Product Engine as Computing Memory to Accelerate Machine Learning Algorithms," Tsinghua University, Beijing, China, Mar. 27, 2016.

3. "Dot-Product Engine as Computing Memory to Accelerate Machine Learning Algorithms," 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, Mar. 16, 2016.

B. Patents:

A) Patents Granted

1. J. P. Strachan, G. E. Montgomery, N. Ge, M. Hu and J. Yang, "Memristive Dot Product Engine with A Nulling Amplifier," US9947405B2, Apr. 17, 2018.

2. M. Hu, J. P. Strachan and N. Muralimanohar, "Convolution Accelerators," US10042819B2, Aug. 7, 2018.

3. M. Hu, J. P. Strachan, N. Ge and J. Yang, "Resistive elements to operate as a matrix of probabilities," US9847124B2, Dec. 19, 2017.

4. Q. Wu, R. Linderman, G. Rose, H. Li, Y. Chen and M. Hu, "Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems," US patent 9,715,655, Jul. 25, 2017.

5. R. Linderman, Q. Wu, G. Rose, H. Li, Y. Chen and M. Hu, "Apparatus for Performing Matrix Vector Multiplication Approximation using Crossbar Arrays of Resistive Memory Devices," US13/965459, Oct. 6, 2015.

B) Patents Pending

1. M. Hu, J. P. Strachan, Z. Li and R. S. Williams, "Linear Transformation Accelerators," PCT/US2016/018567, filed on February 19, 2016.

2. J. P. Strachan, M. Hu, R. S. Williams, and Z. Li, "Memristor Crossbar Array for Performing a Fourier Transformation," PCT/US2016/015429, filed on January 28, 2016.

3. M. Hu, J. Huang, C. Chen, R. G. Beausoleil and J. P. Strachan, "Memristor crossbar arrays to activate processors," US2015/066902, filed on December 18, 2015.

4. M. Hu, J. P. Strachan, Z. Li and R. S. Williams, "Improved Computational Accuracy in a Crossbar System," PCT/US2015/066371, filed on December 17, 2015.

5. M. Hu, Z. Li and J. P. Strachan, "1T1M Crossbar Arrays for Calculating Matrix Multiplication," PCT/US2015/052262, filed on September 25, 2015.

6. M. Hu, J. P. Strachan, Z. Li and R. S. Williams, "Crossbar Arrays for Calculating Matrix Multiplication," PCT/US2015/044246, filed on August 7, 2015.

7. J. P. Strachan, M. Hu and S. Kumar, "Memristor Array with Active Memristors Having a Variable Transmission Delay," PCT/US2015/040877, filed on July 17, 2015.

8. M. Hu, G. Gibson, J. P. Strachan and N. Ge, "Hybrid Selectors," PCT/US2015/032117, filed on May 22 2015.

9. M. Hu, N. Ge, J. P. Strachan and R. S. Williams, "Memristor apparatus with variable transmission delay," PCT/US2015/028044, filed on April 28, 2015.

10. M. Hu, J. P. Strachan, N. Ge and J. Yang, "Resistive Elements to Operate as a Matrix of Probabilities," PCT/US2015/027284, filed on April 23, 2015.

11. N. Ge, J. Yang, M. Hu and J. P. Strachan, "Temperature Compensation Circuits," PCT/US2015/025450, filed on April 10, 2015.

12. N. Ge, J. Yang, J. P. Strachan and M. Hu, "Nonvolatile Memory Cross-bar Array," PCT/US1014/070266, filed on December 15, 2014.

13. M. Hu, J. Yang and N. Ge, "Device with Multiple Resistance Switches with Different Switching Characteristics," PCT/US2014/063667, filed on November 3, 2014.

14. M. Hu, J. Yang, J. P. Strachan and N. Ge, "Double Bias Memristive Dot Product Engine for Vector Processing," PCT/US2014/063213, filed on October 30, 2014.

15. J. Yang, M. Hu, J. P. Strachan and N. Ge, "Memristive Dot Product Engine for Vector Processing," PCT/US2014/062977, filed on October 29, 2014.

16. N. Ge, J. P. Strachan, J. Yang and M. Hu, "Memcapacitive Cross-bar Array for Determining a Dot Product," PCT/US2014/062694, filed on October 28, 2014.

17. N. Ge, J. Yang, J. P. Strachan and M. Hu, "Memristive Cross-bar Array for Determining a Dot Product," PCT/US2014/062010, filed on October 23, 2014.